NoC中串并联链路的比较分析

2004 International Symposium on System-on-Chip, 2004. Proceedings. Pub Date : 2004-11-16 DOI:10.1109/ISSOC.2004.1411181

A. Morgenshtein, I. Cidon, A. Kolodny, R. Ginosar

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引用次数: 61

摘要

采用解析模型对NoC互连中的串行和并行通信技术进行了表征和比较。基于130 nm和70 nm技术参数的仿真显示，与32位多层并行链路相比，串行链路的功耗和面积分别降低了5.5倍和17倍。单层并联链路功耗较低，但占用面积较大。我们的结论是，长片上互连可以受益于串行链路。

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Comparative analysis of serial vs parallel links in NoC

An analytical model is employed to characterize and compare serial and parallel communication techniques in NoC interconnects. Simulations that are based on 130 nm and 70 nm technology parameters reveal up to /spl times/5.5 and /spl times/17 reduction in power and area of serial vs. 32-bit multi-layer parallel links, respectively. Lower power is dissipated by a single-layer parallel link but it occupies a larger area. We conclude that long on-chip interconnects could benefit from serial links.

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2004 International Symposium on System-on-Chip, 2004. Proceedings.

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