FIR filter implementation on FPGA using MCM design technique

Finite Impulse Response (FIR) Filter is filtering whose impulse response is of finite duration. A Higher order of FIR filter is required for meeting precise frequency specification in several digital signal processing applications. But the number of additions and multiplications increase linearly with filter length leading to computational complexity. So a less complex Multiple Constant Multiplication design techniques are used for designing FIR filter in which given input is multiplied with the set of constants. It basically reduces the number of additions required for realization of multiplication. Thus it is suitable for large order FIR filter with fixed coefficients. Block processing along with transpose form of FIR filter is used to support pipelining and higher sampling rate. Power efficient Spartan 6 FPGA logic family is used for hardware implementation. Thus implemented structure provides an area and power efficient high-performance design of FIR filter with reduced computational complexity for both fixed and reconfigurable application.