大容量dram分布式串行多比特并行测试方案

Symposium 1993 on VLSI Circuits Pub Date : 1993-05-19 DOI:10.1109/VLSIC.1993.920538

T. Sugibayashi, T. Takeshima, I. Naritake, T. Matano, H. Takada, Y. Aimoto, M. Fujita

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摘要

本文提出了一种适用于大容量dram的分布式串行多比特并行测试方案。它实现了高并行测试比特数，并且对于单元和感测放大器而言，具有与正常模式相同的操作裕度。此外，它对测试模式施加了很少的限制。该方案已在实验性256Mb DRAM上成功实现了512位并行测试。

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A distributive serial multi-bit parallel test scheme for large capacity DRAMs

This paper describes a distributive serial multi-bit parallel test scheme suitable for large capacity DRAMs. It achieves a high parallel test bit number and, with regard to cells and sense amplifiers, the same operational margin as normal mode. Further, it imposes little restriction on test patterns. The scheme has successfully achieved a 512 bit parallel test on an experimental 256Mb DRAM.

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Symposium 1993 on VLSI Circuits

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