0.18 μm CMOS工艺下MCML与PFSCL栅极的性能比较

2011 2nd International Conference on Computer and Communication Technology (ICCCT-2011) Pub Date : 2011-11-10 DOI:10.1109/ICCCT.2011.6075165

K. Gupta, Ranjana Sridhar, Jaya Chaudhary, N. Pandey, Maneesha Gupta

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引用次数: 8

摘要

本文研究了两种流行的源耦合逻辑形式，即MOS电流模式逻辑(MCML)和正反馈源耦合逻辑(PFSCL)的性能。采用0.18 μm CMOS工艺参数进行了多次SPICE仿真运行。PFSCL电路在传输延迟和面积方面都优于MCML电路。然而，通过蒙特卡罗模拟，过程变化的影响显示MCML电路风格的变化较小。

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Performance comparison of MCML and PFSCL gates in 0.18 μm CMOS technology

In this paper, the performance of two popular source coupled logic styles, namely, MOS Current Mode Logic (MCML) and Positive Feedback Source Coupled Logic (PFSCL) is investigated. A number of SPICE simulation runs have been carried out using 0.18 μm CMOS technology parameters. The PFSCL circuit show better results than the MCML circuit in terms of propagation delay and area. The effect of process variations through Monte Carlo simulations however shows lower variations in MCML circuits style.

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来源期刊

2011 2nd International Conference on Computer and Communication Technology (ICCCT-2011)

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