维特比解码器的实现方案

Proceedings of the Fifteenth National Radio Science Conference. NRSC '98 (Cat. No.98EX109) Pub Date : 1998-02-24 DOI:10.1109/NRSC.1998.711484

M. Aboul-Dahab, M. Ashry, S. A. Salih, M.E. Abd-El-Galil

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引用次数: 0

摘要

本文提出了一种维特比解码器的实现方案。实现过程基于内存管理的回溯算法。利用Craftsman Xilinx软件包，对约束长度k=3、速率r=1/2的卷积编码消息进行了计算机仿真。取得了令人鼓舞的成果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An implementation scheme for a Viterbi decoder

This paper presents a proposed scheme for the implementation of a Viterbi decoder. The implementation process is based upon a trace back algorithm for memory management. Computer simulation of the proposed implementation has been carried out for decoding convolutionally coded messages with constraint length k=3 and rate r=1/2 using the Craftsman Xilinx package. Encouraging results were obtained.

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Proceedings of the Fifteenth National Radio Science Conference. NRSC '98 (Cat. No.98EX109)

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