利用处理器间中断实现推测并行离散事件仿真中的虚拟时间协调

Emiliano Silvestri, Cristian Milia, Romolo Marotta, Alessandro Pellegrini, F. Quaglia
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引用次数: 1

摘要

在推测并行离散事件模拟(PDES)中,当因果错误发生时,减少资源使用(例如,cpu周期)的浪费仍然是一个核心目标。在本文中,我们将在运行在共享内存机器上的推测性PDES上下文中实现这一目标。我们提出了一种基于利用现成硬件芯片组提供的处理器间中断(IPI)设施的操作系统方法,它允许跨cpu核心控制线程的执行流。一旦线程T产生一个新的事件,该事件放置在当前由另一个线程T'运行的模拟对象的过去虚拟时间中,我们基于ip的支持允许T以非常小的延迟更改T'的执行流,从而启用当前处理(不再一致)事件的早期挤压。我们的解决方案对应用程序级别的代码是完全透明的,并与基于轻量级启发式的机制相结合,该机制根据正在处理的错误事件的预期剩余执行时间,通过IPI(而不是跳过IPI发送)确定终止线程T'的实际好处。我们将我们的建议集成到推测的开源USE (Ultimate Share Everything) PDES包中,并报告了在配备32和24(48个超线程)cpu内核的两种共享内存硬件架构上运行各种PDES模型获得的实验结果,证明了我们建议的有效性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Exploiting Inter-Processor-Interrupts for Virtual-Time Coordination in Speculative Parallel Discrete Event Simulation
Reducing the waste of resource usage (e.g., CPU-cycles) when a causality error occurs in speculative parallel discrete event simulation (PDES) is still a core objective. In this article, we target this objective in the context of speculative PDES run on top of shared-memory machines. We propose an Operating System approach that is based on the exploitation of the Inter-Processor-Interrupt (IPI) facility offered by off-the-shelf hardware chipsets, which enables cross-CPU-core control of the execution flow of threads. As soon as a thread T produces a new event placed in the past virtual time of a simulation object currently run by another thread T', our IPI-based support allows T to change the execution flow of T'---with very minimal delay---so to enable the early squash of the currently processed (and no longer consistent) event. Our solution is fully transparent to the application level code, and is coupled with a lightweight heuristic-based mechanism that determines the actual goodness of killing thread T' via the IPI (rather than skipping the IPI send) depending on the expected residual execution time of the incorrect event being processed. We integrated our proposal within the speculative open-source USE (Ultimate Share Everything) PDES package, and we report experimental results obtained by running various PDES models on top of two shared-memory hardware architectures equipped with 32 and 24 (48 Hyper-threads) CPU-cores, which demonstrate the effectiveness of our proposal.
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