Fast IDCT implementation on hardware accelerator devices

Most of hyhrid morion compensated video codiiig staudards rise a well known discrete cosirie traiisform (DCT) at the encoder to remove reduridancy from video raudom processes. An inverse operurion takes place at the decoder. As all crrlculutioris ore done in floating point. some carefully design is nerded when calculations are implemented in j k e d p i n / circrrirs. This paper proposes a hish peformunce IDCT algorithm and its implementation usiiig a FPGA. IDCT is one of the most compuration-iiitensive part.s .f the video coding process. For this reason. a fus t hardware based IDCT iriiplementution is crucial to speed-up video processing. I . Index Terms IDCT, Fixed-point Processing, Hardware Accelerators, FPGA