A Switched Capacitor Multilevel Inverter with Self Voltage Balancing Capability

A modified structure of a switched capacitor included multilevel inverter (SCMLI) is discussed in this paper. The proposed structure is presented with the aim to reduce the total switches. 13-level output is achieved by using 9 switches and 1 capacitor. Moreover, the additional features of the proposed structure include the self-balanced capacitor voltage, reduced total standing voltage (TSV) and output of both polarities without using an H-bridge. Simulation results showing the voltage and current waveforms for different loading conditions are included. The comparison section in the paper is present to compare the presented topology with the other inverter topologies. Results are also taken for a dynamic change in modulation index and loading conditions. MATLAB/SIMULINK is used for obtaining the simulation results, which is validated by hardware in loop implementation of the proposed topology. With the help of loss analysis, efficiency of the proposed structure is calculated. This is done by using PLECS software. The proposed topology has the maximum efficiency of 98.8 %.