Modeling shared-memory ATM switches with fluid-flow models

Shared-memory switches are developing as the principal switch architecture in ATM networks. This has created demand for efficient and accurate methods of analysis. But the increase in memory sizes used in switches make existing forms of analysis too computationally intensive. Fluid flow models do not include the buffer content in their states and therefore the number of states is buffer independent. This paper critically reviews existing fluid-flow models for shared-memory switches. The advantages of each model are used in developing a model that accurately and efficiently provides cell loss and delay values. The performance of the proposed model is compared with results obtained via simulation and other fluid-flow models. The number of states and the computational time of the fluid-flow models are significantly less than traditional discrete queuing models.