Performance analysis of Silicon-On-Nothing MOSFET under 100nm technology nodes

In this paper, we inspect and analyze the performance, electrical response and schematic of silicon-on-nothing MOSFET at 45nm and 35nm channel length by utilizing Silvaco TCAD simulator. Eventually, the parameter extraction analysis is experienced in terms of leakage current, trans-conductance, Drain Induced Barrier Lowering (DIBL), threshold voltage and on-off current ratio. Although, the main advantage of simulating SON MOSFET is that it works efficiently for sub 100nm technology nodes and minimizes short channel effects (SCE) upto greater extent. Additionally, SON MOSFET gives minimum power dissipation, lesser leakage current, and minimizes self-heating issues by incorporating an air dielectric layer which have lower dielectric value in comparison to Silicon dioxide dielectric layer. The main reason for finding an alternative for MOSFET is that, in MOSFET it is immensely unfortunate to get minimum leakage current value and lower length for the channel layer. Therefore, SON structure is incorporated in-place of bulk MOSFET that overcomes all these problems below 100nm channel length. Also, due to rapid and continuous development in the nanotechnology research area, it is extremely essential to have smaller size of semiconductor devices so that they generate better outcomes at different nanotechnology nodes, i.e. 60nm, 50nm, 45nm, 35nm, 30nm, 22nm etc. In future research, SON MOSFET will provide the best alternative to semiconductor and nanotechnology industry.