模集{2n, 2n+1-1, 2n-1}的新型反变换器设计

Yuan-Ching Kuo, M. Sheu, S. Siao, Cheng Huang, Tzu-Hsuing Chen
{"title":"模集{2n, 2n+1-1, 2n-1}的新型反变换器设计","authors":"Yuan-Ching Kuo, M. Sheu, S. Siao, Cheng Huang, Tzu-Hsuing Chen","doi":"10.1109/IBICA.2011.66","DOIUrl":null,"url":null,"abstract":"An efficient design of the reverse converter forthe three-moduli set {2n, 2n+1-1, 2n-1} is presented in thispaper. The reverse converter  is structured by an adderbased on New Chinese Remainder Theorem II (NewCRT-II) conversion such that it can improve thehardware cost. The proposed conversion design iscompared with the existing works based on the standardCell TSMC 0.18µm CMOS technology. Under the samedynamic range(DR), the experimental results indicatethat our design has better performance in terms of thearea×  delay  ×  power. The proposed converter canachieve about average 46.596 % and 61.890 % reductionfor those design with 4n-bit and 5n-bit dynamic range,respectively.","PeriodicalId":158080,"journal":{"name":"2011 Second International Conference on Innovations in Bio-inspired Computing and Applications","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"New Reverse Converter Design of Moduli Set {2n, 2n+1-1, 2n-1}\",\"authors\":\"Yuan-Ching Kuo, M. Sheu, S. Siao, Cheng Huang, Tzu-Hsuing Chen\",\"doi\":\"10.1109/IBICA.2011.66\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An efficient design of the reverse converter forthe three-moduli set {2n, 2n+1-1, 2n-1} is presented in thispaper. The reverse converter  is structured by an adderbased on New Chinese Remainder Theorem II (NewCRT-II) conversion such that it can improve thehardware cost. The proposed conversion design iscompared with the existing works based on the standardCell TSMC 0.18µm CMOS technology. Under the samedynamic range(DR), the experimental results indicatethat our design has better performance in terms of thearea×  delay  ×  power. The proposed converter canachieve about average 46.596 % and 61.890 % reductionfor those design with 4n-bit and 5n-bit dynamic range,respectively.\",\"PeriodicalId\":158080,\"journal\":{\"name\":\"2011 Second International Conference on Innovations in Bio-inspired Computing and Applications\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 Second International Conference on Innovations in Bio-inspired Computing and Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IBICA.2011.66\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Second International Conference on Innovations in Bio-inspired Computing and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IBICA.2011.66","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

本文针对三模集{2n, 2n+1-1, 2n-1}给出了一种有效的反变换器设计。该反向转换器采用基于新中文剩余定理II (NewCRT-II)转换的加法器结构,从而提高了硬件成本。将所提出的转换设计与基于标准cell TSMC 0.18µm CMOS技术的现有工作进行了比较。在相同的动态范围(DR)下,实验结果表明,我们的设计在面积×延迟×功率方面具有更好的性能。对于采用4n-bit和5n-bit动态范围的设计,所提出的转换器可以分别实现46.596%和61.890%的平均降幅。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
New Reverse Converter Design of Moduli Set {2n, 2n+1-1, 2n-1}
An efficient design of the reverse converter forthe three-moduli set {2n, 2n+1-1, 2n-1} is presented in thispaper. The reverse converter  is structured by an adderbased on New Chinese Remainder Theorem II (NewCRT-II) conversion such that it can improve thehardware cost. The proposed conversion design iscompared with the existing works based on the standardCell TSMC 0.18µm CMOS technology. Under the samedynamic range(DR), the experimental results indicatethat our design has better performance in terms of thearea×  delay  ×  power. The proposed converter canachieve about average 46.596 % and 61.890 % reductionfor those design with 4n-bit and 5n-bit dynamic range,respectively.
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