A. Mineyama, Hiroyuki Ito, T. Ishii, K. Okada, K. Masu
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LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process
This paper demonstrates a low voltage differential signaling (LVDS)-type on-chip transmission line (TL) interconnect to solve delay issues on global interconnects. The proposed on-chip TL interconnect can achieve 10.5 Gbps signaling and has smaller delay, smaller delay variation and better power efficiency than conventional on-chip interconnects at high-frequencies.
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