静态CMOS电路中电流可测试故障的测试模式生成

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's Pub Date : 1991-04-15 DOI:10.1109/VTEST.1991.208174

F. Ferguson, T. Larrabee

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引用次数: 5

摘要

静态CMOS电路中的许多制造缺陷无法通过传统的单卡故障模型生成的测试来检测。这些缺陷可能被检测为增加的传播时间或过多的静态电源电流(IDDQ)。在本文中，作者考虑了可能的制造缺陷，并比较了通过由此产生的过量IDDQ检测它们的成本与传统测试方法的成本

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Test pattern generation for current testable faults in static CMOS circuits

Many manufacturing defects in static CMOS circuits are not detected by tests generated using the traditional single stuck-at fault model. May of these defects may be detected as increased propagation time or as excessive quiescent power supply current (IDDQ). In this paper the authors consider the probable manufacturing defects and compare the costs of detecting them by the resulting excess IDDQ versus the cost of traditional testing methods.<>

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Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's

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