3D集成电路系统技术协同优化与设计挑战

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI:10.1109/CICC53496.2022.9772831

Supreet Jeloka, B. Cline, Shidhartha Das, Benoît Labbé, Alejandro Rico, R. Herberholz, Javier A. DeLaCruz, R. Mathur, S. Hung

{"title":"3D集成电路系统技术协同优化与设计挑战","authors":"Supreet Jeloka, B. Cline, Shidhartha Das, Benoît Labbé, Alejandro Rico, R. Herberholz, Javier A. DeLaCruz, R. Mathur, S. Hung","doi":"10.1109/CICC53496.2022.9772831","DOIUrl":null,"url":null,"abstract":"As Moore's law fades and scaling of logic, memory and interconnects diverge, 3D integration technologies have become one of the primary approaches to maintaining performance gains in SoCs and SiPs. To fully exploit the system-level performance gains from 3D, we need to co-optimize the 3D system design for the 3D integration technology used, as well as solve the major physical design challenges of system partitioning, power delivery, thermals, and timing for 3D ICs. In this paper we will cover the system technology co-optimization and design challenges for 3D ICs from high-performance 3D CPU to many-core 3D system design.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"System technology co-optimization and design challenges for 3D IC\",\"authors\":\"Supreet Jeloka, B. Cline, Shidhartha Das, Benoît Labbé, Alejandro Rico, R. Herberholz, Javier A. DeLaCruz, R. Mathur, S. Hung\",\"doi\":\"10.1109/CICC53496.2022.9772831\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As Moore's law fades and scaling of logic, memory and interconnects diverge, 3D integration technologies have become one of the primary approaches to maintaining performance gains in SoCs and SiPs. To fully exploit the system-level performance gains from 3D, we need to co-optimize the 3D system design for the 3D integration technology used, as well as solve the major physical design challenges of system partitioning, power delivery, thermals, and timing for 3D ICs. In this paper we will cover the system technology co-optimization and design challenges for 3D ICs from high-performance 3D CPU to many-core 3D system design.\",\"PeriodicalId\":415990,\"journal\":{\"name\":\"2022 IEEE Custom Integrated Circuits Conference (CICC)\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Custom Integrated Circuits Conference (CICC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC53496.2022.9772831\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Custom Integrated Circuits Conference (CICC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC53496.2022.9772831","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

随着摩尔定律的逐渐消失以及逻辑、内存和互连的扩展分歧，3D集成技术已成为保持soc和sip性能提升的主要方法之一。为了充分利用3D带来的系统级性能提升，我们需要针对所使用的3D集成技术共同优化3D系统设计，并解决3D集成电路的系统分区、功率传输、散热和时序等主要物理设计挑战。在本文中，我们将介绍从高性能3D CPU到多核3D系统设计的3D集成电路的系统技术协同优化和设计挑战。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

System technology co-optimization and design challenges for 3D IC

As Moore's law fades and scaling of logic, memory and interconnects diverge, 3D integration technologies have become one of the primary approaches to maintaining performance gains in SoCs and SiPs. To fully exploit the system-level performance gains from 3D, we need to co-optimize the 3D system design for the 3D integration technology used, as well as solve the major physical design challenges of system partitioning, power delivery, thermals, and timing for 3D ICs. In this paper we will cover the system technology co-optimization and design challenges for 3D ICs from high-performance 3D CPU to many-core 3D system design.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2022 IEEE Custom Integrated Circuits Conference (CICC)

自引率

0.00%

发文量