Efficient test environment for multi-level simulations of mixed-signal systems on chip

The traditional approach for mixed-signal systems is partitioning the design at the beginning of its development cycle: digital and analog portions are then designed and verified separately. The digital design flow is typically top-down, thus allowing a continuous verification of the matching between specification and simulation results. Instead the analog flow is more frequently bottom-up and this makes hard to feedback information from the bottom level simulations to the design top level, being almost impossible SPICE simulations of the whole system (due to the excessive simulation time, convergence troubles and computational effort). This kind of mixed-signal separated flow can easily lead to a final assembly which is not sufficiently tested (such strategy cannot provide the designer with much confidence that digital and analog portions will interface correctly) and thus it's extremely difficult to debug. A full covering test strategy is not allowed also for another reason: many tests are not possible at HDL level, because of the lack of interactivity during simulation process. In fact, if we consider for example a generic calibration sequence, the procedure must assign parameter values depending on DUT state, by changing actions to perform, relating to effects of the previous acted. In this paper we propose a complete environment to test together analog and digital parts by using a semi-automatic VHDL-AMS flow adding the use of Python scripts to drive the simulation, interacting with both Verilog top-level model or real chip, creating a dynamic co-operation for real-time data processing with high re-usability for a fast conditional complete test flow.