Instruction-based March Test Pattern Generation Scheme for At-Speed Test Cost Reduction

A fast-growing manufacturing technology of memory devices leads to further increased design complexity, density and test cost. In general, the high cost of automated test equipment (ATE) is required to test the high-speed memory devices, which can exceed its memory performance. To solve this problem, the manufacturers are seeking more cost-effective methods, especially for at-speed testing. In order to reduce the test cost, we propose the instruction-based march test pattern generation scheme which can be applied to the low-end ATE with multiple pattern generators. The proposed method can generate linear patterns based on instructions, which can distribute them to multiple ALPGs of a low-end ATE to implement the high-speed test patterns. The experimental results show that the various march test patterns for at-speed testing can be implemented by using the several fixed commands, regardless of the memory cell sizes.