一种基于左生长双边缘脉宽调制的无滤波器数字音频d类放大器

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2017-11-01 DOI:10.1109/ICAM.2017.8242175

Xiaolei Chen, Haipeng Qu, Zeqi Yu, Chunyang Zhang, Enguang Zhang

{"title":"一种基于左生长双边缘脉宽调制的无滤波器数字音频d类放大器","authors":"Xiaolei Chen, Haipeng Qu, Zeqi Yu, Chunyang Zhang, Enguang Zhang","doi":"10.1109/ICAM.2017.8242175","DOIUrl":null,"url":null,"abstract":"A filterless digital audio class-D amplifier (CDA) based on grow-Left double-edge (GLDE) pulse width modulation (PWM) is proposed in this paper. It consists of a high performance fully-digital uniform-sampling PWM (UPWM) modulator and a bridge-tied-load (BTL) power stage. Due to adopt the ternary PWM modulation scheme, the filterless solution without LC low-pass filter becomes possible. Finally, the error of the BTL power stage is properly corrected to make this amplifier system have a high power supply rejection ratio (PSRR) and a high signal to noise ratio (SNR). The whole design is implemented on Matlab and Cadence platform, combining with 5V 0.35-μm CMOS process technology.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A filterless digital audio class-D amplifier based on grow-left double-edge pulse width modulation\",\"authors\":\"Xiaolei Chen, Haipeng Qu, Zeqi Yu, Chunyang Zhang, Enguang Zhang\",\"doi\":\"10.1109/ICAM.2017.8242175\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A filterless digital audio class-D amplifier (CDA) based on grow-Left double-edge (GLDE) pulse width modulation (PWM) is proposed in this paper. It consists of a high performance fully-digital uniform-sampling PWM (UPWM) modulator and a bridge-tied-load (BTL) power stage. Due to adopt the ternary PWM modulation scheme, the filterless solution without LC low-pass filter becomes possible. Finally, the error of the BTL power stage is properly corrected to make this amplifier system have a high power supply rejection ratio (PSRR) and a high signal to noise ratio (SNR). The whole design is implemented on Matlab and Cadence platform, combining with 5V 0.35-μm CMOS process technology.\",\"PeriodicalId\":117801,\"journal\":{\"name\":\"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICAM.2017.8242175\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICAM.2017.8242175","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

提出了一种基于左生长双边缘脉宽调制(PWM)的无滤波器数字音频d类放大器。它由一个高性能全数字均匀采样PWM (UPWM)调制器和一个桥系负载(BTL)功率级组成。由于采用了三进制PWM调制方案，使得无需LC低通滤波器的无滤波器解决方案成为可能。最后，对BTL功率级的误差进行了适当的修正，使该放大器系统具有较高的电源抑制比(PSRR)和高信噪比(SNR)。整个设计结合5V 0.35 μm CMOS工艺技术，在Matlab和Cadence平台上实现。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A filterless digital audio class-D amplifier based on grow-left double-edge pulse width modulation

A filterless digital audio class-D amplifier (CDA) based on grow-Left double-edge (GLDE) pulse width modulation (PWM) is proposed in this paper. It consists of a high performance fully-digital uniform-sampling PWM (UPWM) modulator and a bridge-tied-load (BTL) power stage. Due to adopt the ternary PWM modulation scheme, the filterless solution without LC low-pass filter becomes possible. Finally, the error of the BTL power stage is properly corrected to make this amplifier system have a high power supply rejection ratio (PSRR) and a high signal to noise ratio (SNR). The whole design is implemented on Matlab and Cadence platform, combining with 5V 0.35-μm CMOS process technology.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)

自引率

0.00%

发文量