{"title":"可预测的多核架构的PROMPT设计原则","authors":"R. Wilhelm","doi":"10.1145/1543820.1543826","DOIUrl":null,"url":null,"abstract":"Embedded hard real-time systems need reliable guarantees for the satisfaction of their timing constraints. The precision of the results and the efficiency of timing-analysis methods are highly dependent on the predictability of the execution platform.\n The possibility of proving the safety of embedded systems is seriously compromised by architectural developments aiming exclusively at improving average-case performance. Proving the correctness of a modern high-performance processor is beyond the reach of verification methods. Even the chances to derive reliable and precise bounds on execution times are endangered by exactly these developments.\n We propose design principles for multi-core architectures to provide efficiently predictable good worst-case performance as needed for embedded control in the aeronautics and automotive industries supporting the Integrated Modular Avionics (IMA) and the Automotive Open System Architecture (AUTOSAR) development trends. This talk presents a development process oriented at achieving predictability at all levels of the architecture hierarchy.","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"The PROMPT design principles for predictable multi-core architectures\",\"authors\":\"R. Wilhelm\",\"doi\":\"10.1145/1543820.1543826\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Embedded hard real-time systems need reliable guarantees for the satisfaction of their timing constraints. The precision of the results and the efficiency of timing-analysis methods are highly dependent on the predictability of the execution platform.\\n The possibility of proving the safety of embedded systems is seriously compromised by architectural developments aiming exclusively at improving average-case performance. Proving the correctness of a modern high-performance processor is beyond the reach of verification methods. Even the chances to derive reliable and precise bounds on execution times are endangered by exactly these developments.\\n We propose design principles for multi-core architectures to provide efficiently predictable good worst-case performance as needed for embedded control in the aeronautics and automotive industries supporting the Integrated Modular Avionics (IMA) and the Automotive Open System Architecture (AUTOSAR) development trends. This talk presents a development process oriented at achieving predictability at all levels of the architecture hierarchy.\",\"PeriodicalId\":375451,\"journal\":{\"name\":\"Software and Compilers for Embedded Systems\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-04-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Software and Compilers for Embedded Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1543820.1543826\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Software and Compilers for Embedded Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1543820.1543826","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The PROMPT design principles for predictable multi-core architectures
Embedded hard real-time systems need reliable guarantees for the satisfaction of their timing constraints. The precision of the results and the efficiency of timing-analysis methods are highly dependent on the predictability of the execution platform.
The possibility of proving the safety of embedded systems is seriously compromised by architectural developments aiming exclusively at improving average-case performance. Proving the correctness of a modern high-performance processor is beyond the reach of verification methods. Even the chances to derive reliable and precise bounds on execution times are endangered by exactly these developments.
We propose design principles for multi-core architectures to provide efficiently predictable good worst-case performance as needed for embedded control in the aeronautics and automotive industries supporting the Integrated Modular Avionics (IMA) and the Automotive Open System Architecture (AUTOSAR) development trends. This talk presents a development process oriented at achieving predictability at all levels of the architecture hierarchy.