{"title":"一种基于0.3 thz sigb的倍频芯片,具有3db 50ghz带宽和17db峰值转换增益","authors":"Faisal Ahmed, M. Furqan, A. Stelzer","doi":"10.23919/EUMIC.2017.8230678","DOIUrl":null,"url":null,"abstract":"This paper presents a broadband frequency doubler chip working in the WR-03 band (220–325 GHz). The chip is implemented in a 130-nm SiGe BiCMOS technology with an of 250/300 GHz. It consists of an integrated high-gain wideband amplifier to drive the frequency doubler. The doubler is based on a cascode push-push topology. Conversion loss of the doubler is reduced by utilizing an inductive feedback in the common-base stage. A very wideband operation of the doubler is achieved using optimally sized transistors and 4-reactance based input matching network. On-wafer measurement of the chip shows a state-of-the-art 17.4 dB peak conversion gain at 270 GHz. It delivers a maximum output power of almost 1 mW with a 3-dB bandwidth ranging from 257 GHz to 307 GHz, which is the highest bandwidth for Si-based frequency doublers working entirely in the WR-03 band. The chip consumes around 429 mW from a supply voltage of 3.3 V.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 0.3-THz SiGe-based frequency doubler chip with 3-dB 50 GHz bandwidth and 17 dB peak conversion gain\",\"authors\":\"Faisal Ahmed, M. Furqan, A. Stelzer\",\"doi\":\"10.23919/EUMIC.2017.8230678\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a broadband frequency doubler chip working in the WR-03 band (220–325 GHz). The chip is implemented in a 130-nm SiGe BiCMOS technology with an of 250/300 GHz. It consists of an integrated high-gain wideband amplifier to drive the frequency doubler. The doubler is based on a cascode push-push topology. Conversion loss of the doubler is reduced by utilizing an inductive feedback in the common-base stage. A very wideband operation of the doubler is achieved using optimally sized transistors and 4-reactance based input matching network. On-wafer measurement of the chip shows a state-of-the-art 17.4 dB peak conversion gain at 270 GHz. It delivers a maximum output power of almost 1 mW with a 3-dB bandwidth ranging from 257 GHz to 307 GHz, which is the highest bandwidth for Si-based frequency doublers working entirely in the WR-03 band. The chip consumes around 429 mW from a supply voltage of 3.3 V.\",\"PeriodicalId\":120932,\"journal\":{\"name\":\"2017 12th European Microwave Integrated Circuits Conference (EuMIC)\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 12th European Microwave Integrated Circuits Conference (EuMIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/EUMIC.2017.8230678\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/EUMIC.2017.8230678","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.3-THz SiGe-based frequency doubler chip with 3-dB 50 GHz bandwidth and 17 dB peak conversion gain
This paper presents a broadband frequency doubler chip working in the WR-03 band (220–325 GHz). The chip is implemented in a 130-nm SiGe BiCMOS technology with an of 250/300 GHz. It consists of an integrated high-gain wideband amplifier to drive the frequency doubler. The doubler is based on a cascode push-push topology. Conversion loss of the doubler is reduced by utilizing an inductive feedback in the common-base stage. A very wideband operation of the doubler is achieved using optimally sized transistors and 4-reactance based input matching network. On-wafer measurement of the chip shows a state-of-the-art 17.4 dB peak conversion gain at 270 GHz. It delivers a maximum output power of almost 1 mW with a 3-dB bandwidth ranging from 257 GHz to 307 GHz, which is the highest bandwidth for Si-based frequency doublers working entirely in the WR-03 band. The chip consumes around 429 mW from a supply voltage of 3.3 V.