VLSI中电容矩阵直接提取的测试结构

ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307) Pub Date : 1999-03-15 DOI:10.1109/ICMTS.1999.766243

T. Mido, H. Ito, K. Asada

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引用次数: 3

摘要

提出了一种用于直接提取多层互连电容矩阵分量的新型测试结构。该方法直接从测量数据中获取各分量作为驱动单元与参考单元的电流值之差，无需进行任何计算，并且与目标矩阵的大小无关，总焊盘保持在8。通过对结构不对称引起的测量误差的评估，该方法能够以飞法拉阶精度测量电容矩阵的分量。

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Test structure for direct extraction of capacitance matrix in VLSI

A compact new test structure for direct extraction of components of the capacitance matrix for multilayer interconnections is presented. In this new method, each component is directly obtained from the measurement data without any calculation as the difference between current values for driver unit and reference unit, and the total pads are kept at 8 independently of the size of target matrix. As a result of evaluation of measurement errors due to the asymmetry of the structures, this new method can measure components of capacitance matrix with femto-farad order precision.

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来源期刊

ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)

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