{"title":"一个1.2V 440-MS/s 0.13µm CMOS流水线模数转换器，具有5-8bit模式选择","authors":"Tero Nieminen, K. Halonen","doi":"10.1109/NORCHIP.2010.5669463","DOIUrl":null,"url":null,"abstract":"In this paper, an 8-bit (with 5-8bit mode selection), 440-MS/s pipelined Analog-to-Digital Converter (ADC) is presented. The ADC utilizes double-sampling in order to relax the operational amplifier (opamp) settling time requirements. Redundant sign digit (RSD) correction compensates offset errors of the comparators. The ADC is designed with a 0.13-µm CMOS process. In the 8-bit mode, measured effective number of bits (ENOB) of the ADC is 6.10 with 162-MHz full-scale input, while the current drawn from 1.2V supply is 83mA.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"An 1.2V 440-MS/s 0.13-µm CMOS pipelined Analog-to-Digital Converter with 5-8bit mode selection\",\"authors\":\"Tero Nieminen, K. Halonen\",\"doi\":\"10.1109/NORCHIP.2010.5669463\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, an 8-bit (with 5-8bit mode selection), 440-MS/s pipelined Analog-to-Digital Converter (ADC) is presented. The ADC utilizes double-sampling in order to relax the operational amplifier (opamp) settling time requirements. Redundant sign digit (RSD) correction compensates offset errors of the comparators. The ADC is designed with a 0.13-µm CMOS process. In the 8-bit mode, measured effective number of bits (ENOB) of the ADC is 6.10 with 162-MHz full-scale input, while the current drawn from 1.2V supply is 83mA.\",\"PeriodicalId\":292342,\"journal\":{\"name\":\"NORCHIP 2010\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-12-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"NORCHIP 2010\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NORCHIP.2010.5669463\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"NORCHIP 2010","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NORCHIP.2010.5669463","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An 1.2V 440-MS/s 0.13-µm CMOS pipelined Analog-to-Digital Converter with 5-8bit mode selection
In this paper, an 8-bit (with 5-8bit mode selection), 440-MS/s pipelined Analog-to-Digital Converter (ADC) is presented. The ADC utilizes double-sampling in order to relax the operational amplifier (opamp) settling time requirements. Redundant sign digit (RSD) correction compensates offset errors of the comparators. The ADC is designed with a 0.13-µm CMOS process. In the 8-bit mode, measured effective number of bits (ENOB) of the ADC is 6.10 with 162-MHz full-scale input, while the current drawn from 1.2V supply is 83mA.
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