RapidSmith 2:基于Xilinx fpga的bel级CAD探索框架

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays Pub Date : 2015-02-22 DOI:10.1145/2684746.2689085

Travis Haroldsen, B. Nelson, B. Hutchings

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引用次数: 25

摘要

RapidSmith是一个开源框架，允许探索用于Xilinx设备的FPGA CAD流的新方法。然而，RapidSmith对于在切片级别以下操纵设计的支持很差。在本文中，我们重点介绍了RapidSmith支持的许多项目，并将扩展合并到“RapidSmith 2”中，这些扩展暴露了lut和触发器，以便在定制的CAD工具中直接操作。为了演示RapidSmith 2的实用性，我们展示了在设计中识别必须聚集在一起的bel的工作结果，以及相应的预打包聚类工具。

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RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs

RapidSmith is an open-source framework that allows for the exploration of novel approaches to the FPGA CAD flow for Xilinx devices. However, RapidSmith has poor support for manipulating designs below the slice level. In this paper, we highlight many of the projects RapidSmith enables and present extensions incorporated into "RapidSmith 2" that expose LUTs and flip-flops for direct manipulation in custom-built CAD tools. To demonstrate the utility of RapidSmith 2 we present the results of work to identify BELs in a design which must be clustered together and a tool that does pre-packing clustering accordingly.

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Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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