高速比较器的设计与分析

2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks Pub Date : 1900-01-01 DOI:10.1109/RFIT.2005.1598914

Gu Jun, Li Yong, S. Bo

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引用次数: 4

摘要

本文介绍了一种基于主从结构的超高速双极比较器的设计与分析。该比较器可用于高速数据转换器的设计。采用主从结构改善了亚稳性能，降低了最小差分输入电压。该比较器采用0.35-/spl mu/m SiGe BiCMOS工艺，功耗约为70 mW，采样速度为16 GHz，峰值可分辨最小输入电压为8 mV。

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Design and analysis of a high-speed comparator

This paper presents the design and analysis of an ultra high-speed bipolar comparator based on master-slave architecture. The comparator can be used for very high speed data converters design. Master-slave structure is used to improve metastability behavior and reduce minimum differential input voltage. Implemented in a 0.35-/spl mu/m SiGe BiCMOS process, the comparator consumes approximately 70 mW with sampling speed of 16 GHz and resolvable minimum input voltage of 8 mV peak-to-peak.

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2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks

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