A reconfigurable SAT-based automatic test pattern generator

With the increasing complexity of integrated circuits and transition to Systems-on-Chip (SoC) paradigm, Automatic Test pattern Generation (ATPG) becomes a crucial tool in the Electronic Design Automation (EDA) domain. ATPG based on Boolean Satisfiability (SAT) has been proposed as an alternative to classical structural algorithms for generating test patterns for single stuck-at faults in combinational circuits. SAT-based ATPG provides excellent balance of simplicity and robustness versus structural algorithms. However, a highly efficient and fast SAT solver in needed to overcome the time overhead incurred in extracting the SAT formula. In this paper, we propose a reconfigurable hardware SAT-based test pattern generator. For different circuits, compilation, synthesis and place-and-route overhead is eliminated. We demonstrate the feasibility of our approach by experimenting with ISCAS'85. Our proposed reconfigurable SAT-based test pattern generator achieves 20 times average speedup compared to software SAT-based ATPG.