K. Han, Srikumar Sandeep, Bill Martin, M. Swaminathan
{"title":"配电网寻路建模","authors":"K. Han, Srikumar Sandeep, Bill Martin, M. Swaminathan","doi":"10.1109/EDAPS.2016.7874398","DOIUrl":null,"url":null,"abstract":"In this paper an algorithm is described for obtaining the response of Power Distribution Networks (PDN) arising in chip, package or pcb during an early design phase. Results are provided for power grids arising in silicon interposers to validate the approach.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Modeling of power distribution networks for path finding\",\"authors\":\"K. Han, Srikumar Sandeep, Bill Martin, M. Swaminathan\",\"doi\":\"10.1109/EDAPS.2016.7874398\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper an algorithm is described for obtaining the response of Power Distribution Networks (PDN) arising in chip, package or pcb during an early design phase. Results are provided for power grids arising in silicon interposers to validate the approach.\",\"PeriodicalId\":191549,\"journal\":{\"name\":\"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDAPS.2016.7874398\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAPS.2016.7874398","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Modeling of power distribution networks for path finding
In this paper an algorithm is described for obtaining the response of Power Distribution Networks (PDN) arising in chip, package or pcb during an early design phase. Results are provided for power grids arising in silicon interposers to validate the approach.