{"title":"基于模块阵列结构的算法半定制VLSI","authors":"M. Kameyama, M. Nomura, T. Higuchi","doi":"10.1109/VLSIC.1991.760098","DOIUrl":null,"url":null,"abstract":"A new arithmetic VLSI array based on signed-digit(SD)[l] arithmetic module is proposed. The module is a universal building block mainly composed of an SD adder. Any arithmetic operations based on addition, subtraction and multiplication can be realized by appropriately specifying the interconnections between the modules. This module array is much more useful for design and fabrication with short turnaround time than gate array. High-speed operations can be expected in the adder-based module independently of the word length. Moreover, multiple-valued bidirectional current-mode circuits are effectively employed for the compact implementation of the SD arithmetic VLSI[2]. I1 Module array The module ( PAM ) is composed of an adder, a partial product geneIator ( PPG ), a sign inverter, two encoders and four wiring blocks ( W1, W2, W3 and W4 ) as shown in Fig. 1. One of the operation modes in the module can be selected by the specification of the wiring blocks, so that any arithmetic systems can be constructed using the modules. In order to realize a high-speed compact module, we introduce radix-4 minimum-redundant SD arithmetic system using the multiplevalued bidirectional current-mode circuits. Any arithmetic circuits can be realized by using the adder-based structure with high degree of parallelism because the carry-propagation chains are eliminated[]] in the SD arithmetic. Therefore, highof the use of the adder-based modules. speed operations can be expected in the module array in spite","PeriodicalId":319036,"journal":{"name":"1991 Symposium on VLSI Circuits","volume":"65 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Arithmetic Semicustom VLSI Based On Module Array Structure\",\"authors\":\"M. Kameyama, M. Nomura, T. Higuchi\",\"doi\":\"10.1109/VLSIC.1991.760098\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new arithmetic VLSI array based on signed-digit(SD)[l] arithmetic module is proposed. The module is a universal building block mainly composed of an SD adder. Any arithmetic operations based on addition, subtraction and multiplication can be realized by appropriately specifying the interconnections between the modules. This module array is much more useful for design and fabrication with short turnaround time than gate array. High-speed operations can be expected in the adder-based module independently of the word length. Moreover, multiple-valued bidirectional current-mode circuits are effectively employed for the compact implementation of the SD arithmetic VLSI[2]. I1 Module array The module ( PAM ) is composed of an adder, a partial product geneIator ( PPG ), a sign inverter, two encoders and four wiring blocks ( W1, W2, W3 and W4 ) as shown in Fig. 1. One of the operation modes in the module can be selected by the specification of the wiring blocks, so that any arithmetic systems can be constructed using the modules. In order to realize a high-speed compact module, we introduce radix-4 minimum-redundant SD arithmetic system using the multiplevalued bidirectional current-mode circuits. Any arithmetic circuits can be realized by using the adder-based structure with high degree of parallelism because the carry-propagation chains are eliminated[]] in the SD arithmetic. Therefore, highof the use of the adder-based modules. speed operations can be expected in the module array in spite\",\"PeriodicalId\":319036,\"journal\":{\"name\":\"1991 Symposium on VLSI Circuits\",\"volume\":\"65 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-05-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1991 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1991.760098\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1991 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1991.760098","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Arithmetic Semicustom VLSI Based On Module Array Structure
A new arithmetic VLSI array based on signed-digit(SD)[l] arithmetic module is proposed. The module is a universal building block mainly composed of an SD adder. Any arithmetic operations based on addition, subtraction and multiplication can be realized by appropriately specifying the interconnections between the modules. This module array is much more useful for design and fabrication with short turnaround time than gate array. High-speed operations can be expected in the adder-based module independently of the word length. Moreover, multiple-valued bidirectional current-mode circuits are effectively employed for the compact implementation of the SD arithmetic VLSI[2]. I1 Module array The module ( PAM ) is composed of an adder, a partial product geneIator ( PPG ), a sign inverter, two encoders and four wiring blocks ( W1, W2, W3 and W4 ) as shown in Fig. 1. One of the operation modes in the module can be selected by the specification of the wiring blocks, so that any arithmetic systems can be constructed using the modules. In order to realize a high-speed compact module, we introduce radix-4 minimum-redundant SD arithmetic system using the multiplevalued bidirectional current-mode circuits. Any arithmetic circuits can be realized by using the adder-based structure with high degree of parallelism because the carry-propagation chains are eliminated[]] in the SD arithmetic. Therefore, highof the use of the adder-based modules. speed operations can be expected in the module array in spite