实现PGI加速器模型

GPGPU-3 Pub Date : 2010-03-14 DOI:10.1145/1735688.1735697

M. Wolfe

{"title":"实现PGI加速器模型","authors":"M. Wolfe","doi":"10.1145/1735688.1735697","DOIUrl":null,"url":null,"abstract":"The PGI Accelerator model is a high-level programming model for accelerators, such as GPUs, similar in design and scope to the widely-used OpenMP directives. This paper presents some details of the design of the compiler that implements the model, focusing on the Planner, the element that maps the program parallelism onto the hardware parallelism.","PeriodicalId":381071,"journal":{"name":"GPGPU-3","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"186","resultStr":"{\"title\":\"Implementing the PGI Accelerator model\",\"authors\":\"M. Wolfe\",\"doi\":\"10.1145/1735688.1735697\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The PGI Accelerator model is a high-level programming model for accelerators, such as GPUs, similar in design and scope to the widely-used OpenMP directives. This paper presents some details of the design of the compiler that implements the model, focusing on the Planner, the element that maps the program parallelism onto the hardware parallelism.\",\"PeriodicalId\":381071,\"journal\":{\"name\":\"GPGPU-3\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-03-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"186\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"GPGPU-3\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1735688.1735697\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"GPGPU-3","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1735688.1735697","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 186

摘要

PGI加速器模型是加速器的高级编程模型,如gpu,类似于设计和范围广泛使用OpenMP指令。本文介绍了实现该模型的编译器设计的一些细节，重点介绍了Planner，它是将程序并行性映射到硬件并行性的元素。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Implementing the PGI Accelerator model

The PGI Accelerator model is a high-level programming model for accelerators, such as GPUs, similar in design and scope to the widely-used OpenMP directives. This paper presents some details of the design of the compiler that implements the model, focusing on the Planner, the element that maps the program parallelism onto the hardware parallelism.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

GPGPU-3

自引率

0.00%

发文量