{"title":"尺度沟道长度对纳米级场效应管性能的影响","authors":"J. K. Saha, N. Chakma, M. Hasan","doi":"10.1109/ICECE.2016.7853871","DOIUrl":null,"url":null,"abstract":"The investigation of short-channel effects (SCE) due to channel length reduction for four different types of n-channel FETs: Bulk MOSFET, SOI MOSFET, DG MOSFET and CNTFET are carried out in this work. Simulators are used to investigate SCEs like threshold voltage (V<inf>th</inf>) roll-off, subthreshold Swing (SS) and I<inf>on</inf>/I<inf>off</inf> ratio. Our study shows that DG MOSFET, SOI MOSFET and Bulk MOSFET reach their scalable limit at 30 nm, 50 nm and 100 nm channel length respectively due to elevation of leakage power consumption as they exhibit rapid degradation of V<inf>th</inf>, SS beyond 100mV/decade and less I<inf>on</inf>/I<inf>off</inf> ratio. On the contrary, CNTFET can be scaled down below 10 nm as it shows negligible SCEs with stable V<inf>th</inf>, ideal SS (60mV/decade) and high I<inf>on</inf>/I<inf>off</inf> ratio as channel length decreases. Our numerical analysis shows CNTFET creates only 1.11% V<inf>th</inf> variation whereas DG MOSFET creates 39.33% V<inf>th</inf> variation. CNTFETs advantages over MOSFET make it viable for faster and enhanced applications in nanoelectronics.","PeriodicalId":122930,"journal":{"name":"2016 9th International Conference on Electrical and Computer Engineering (ICECE)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Impact of scaling channel length on the performances of nanoscale FETs\",\"authors\":\"J. K. Saha, N. Chakma, M. Hasan\",\"doi\":\"10.1109/ICECE.2016.7853871\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The investigation of short-channel effects (SCE) due to channel length reduction for four different types of n-channel FETs: Bulk MOSFET, SOI MOSFET, DG MOSFET and CNTFET are carried out in this work. Simulators are used to investigate SCEs like threshold voltage (V<inf>th</inf>) roll-off, subthreshold Swing (SS) and I<inf>on</inf>/I<inf>off</inf> ratio. Our study shows that DG MOSFET, SOI MOSFET and Bulk MOSFET reach their scalable limit at 30 nm, 50 nm and 100 nm channel length respectively due to elevation of leakage power consumption as they exhibit rapid degradation of V<inf>th</inf>, SS beyond 100mV/decade and less I<inf>on</inf>/I<inf>off</inf> ratio. On the contrary, CNTFET can be scaled down below 10 nm as it shows negligible SCEs with stable V<inf>th</inf>, ideal SS (60mV/decade) and high I<inf>on</inf>/I<inf>off</inf> ratio as channel length decreases. Our numerical analysis shows CNTFET creates only 1.11% V<inf>th</inf> variation whereas DG MOSFET creates 39.33% V<inf>th</inf> variation. CNTFETs advantages over MOSFET make it viable for faster and enhanced applications in nanoelectronics.\",\"PeriodicalId\":122930,\"journal\":{\"name\":\"2016 9th International Conference on Electrical and Computer Engineering (ICECE)\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 9th International Conference on Electrical and Computer Engineering (ICECE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECE.2016.7853871\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 9th International Conference on Electrical and Computer Engineering (ICECE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECE.2016.7853871","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Impact of scaling channel length on the performances of nanoscale FETs
The investigation of short-channel effects (SCE) due to channel length reduction for four different types of n-channel FETs: Bulk MOSFET, SOI MOSFET, DG MOSFET and CNTFET are carried out in this work. Simulators are used to investigate SCEs like threshold voltage (Vth) roll-off, subthreshold Swing (SS) and Ion/Ioff ratio. Our study shows that DG MOSFET, SOI MOSFET and Bulk MOSFET reach their scalable limit at 30 nm, 50 nm and 100 nm channel length respectively due to elevation of leakage power consumption as they exhibit rapid degradation of Vth, SS beyond 100mV/decade and less Ion/Ioff ratio. On the contrary, CNTFET can be scaled down below 10 nm as it shows negligible SCEs with stable Vth, ideal SS (60mV/decade) and high Ion/Ioff ratio as channel length decreases. Our numerical analysis shows CNTFET creates only 1.11% Vth variation whereas DG MOSFET creates 39.33% Vth variation. CNTFETs advantages over MOSFET make it viable for faster and enhanced applications in nanoelectronics.