{"title":"基于0.18 μm SiGe BiCMOS技术的40gb /s NRZ无电感跨阻放大器","authors":"H. Hsu, Xuan-Yi Ye, Jau‐Ji Jou, Tien-Tsorng Shih","doi":"10.1109/ISPACS51563.2021.9650922","DOIUrl":null,"url":null,"abstract":"In this study, an inductorless broadband transimpedance amplifier (TIA) is implemented using TSMC 0.18-μm SiGe BiCMOS technology. The regulated cascade circuit is used for the input stage of the TIA. The core amplifier is a fully differential amplifier paralleling with a differentiator that is capable of enhancing the bandwidth of the TIA. The TIA has a differential transimpedance gain of 39.4 dBΩ, a bandwidth of 32.9 GHz, and an average input-referred current noise density of 37 pA/√Hz. The TIA has a power consumption of 77 mW with a supply voltage of 3.3 V, and the chip area is 0.45 mm2 including pads. In the chip testing, the 25- and 40-Gb/s non-return-to-zero eye diagrams are measured and sufficiently clear.","PeriodicalId":359822,"journal":{"name":"2021 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 40-Gb/s NRZ Inductorless Transimpedance Amplifier in a 0.18-μm SiGe BiCMOS Technology\",\"authors\":\"H. Hsu, Xuan-Yi Ye, Jau‐Ji Jou, Tien-Tsorng Shih\",\"doi\":\"10.1109/ISPACS51563.2021.9650922\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this study, an inductorless broadband transimpedance amplifier (TIA) is implemented using TSMC 0.18-μm SiGe BiCMOS technology. The regulated cascade circuit is used for the input stage of the TIA. The core amplifier is a fully differential amplifier paralleling with a differentiator that is capable of enhancing the bandwidth of the TIA. The TIA has a differential transimpedance gain of 39.4 dBΩ, a bandwidth of 32.9 GHz, and an average input-referred current noise density of 37 pA/√Hz. The TIA has a power consumption of 77 mW with a supply voltage of 3.3 V, and the chip area is 0.45 mm2 including pads. In the chip testing, the 25- and 40-Gb/s non-return-to-zero eye diagrams are measured and sufficiently clear.\",\"PeriodicalId\":359822,\"journal\":{\"name\":\"2021 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-11-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPACS51563.2021.9650922\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPACS51563.2021.9650922","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 40-Gb/s NRZ Inductorless Transimpedance Amplifier in a 0.18-μm SiGe BiCMOS Technology
In this study, an inductorless broadband transimpedance amplifier (TIA) is implemented using TSMC 0.18-μm SiGe BiCMOS technology. The regulated cascade circuit is used for the input stage of the TIA. The core amplifier is a fully differential amplifier paralleling with a differentiator that is capable of enhancing the bandwidth of the TIA. The TIA has a differential transimpedance gain of 39.4 dBΩ, a bandwidth of 32.9 GHz, and an average input-referred current noise density of 37 pA/√Hz. The TIA has a power consumption of 77 mW with a supply voltage of 3.3 V, and the chip area is 0.45 mm2 including pads. In the chip testing, the 25- and 40-Gb/s non-return-to-zero eye diagrams are measured and sufficiently clear.