基于65nm CMOS的6.72 gb /s, 8pJ/bit/迭代WPAN LDPC解码器

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI:10.1109/ASPDAC.2013.6509569

Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Leona Okamura, Dajiang Zhou, S. Goto

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引用次数: 3

摘要

提出了一种针对WPAN (IEEE 802.15.3c)的65nm CMOS LDPC解码器，并给出了测量结果。针对LDPC高并行解码带来的网络问题，提出了一种基于改进pcm的兼容数据流的消息排列策略。与目前的技术水平相比，译码芯片在芯片密度、栅极数和能效方面分别提高了17.7%、33.5%和49%。

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A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS

An LDPC decoder in 65nm CMOS targeting WPAN (IEEE 802.15.3c) is presented with measurement results. A modified-PCM based message permutation strategy with compatible data flow is proposed to solve the network problem raised by high parallelism LDPC decoding. Compared to the state-of-art, decoder chip achieves 17.7%, 33.5% and 49% improvements in chip density, gate count and energy efficiency, respectively.

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2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)

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