{"title":"快速ADC电路的新策略","authors":"A. Kelkar, A. Dighe","doi":"10.1109/IMTC.1990.66003","DOIUrl":null,"url":null,"abstract":"A new strategy of successive approximation for fast analog-to-digital converter (ADC) circuits is discussed. A 4-b converter of one-cycle conversion time is first described. The scheme is then modified for flash conversion. The use of a 4-b flash converter in multiplex mode is shown to result in an 8-b converter requiring half-cycle conversion time. The bit subrangeable flash ADC is presented as an attractive proposal. This scheme essentially requires only two major components per bit and uses n identical circuits in cascade for n-b conversion.<<ETX>>","PeriodicalId":404761,"journal":{"name":"7th IEEE Conference on Instrumentation and Measurement Technology","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"New strategies for fast ADC circuits\",\"authors\":\"A. Kelkar, A. Dighe\",\"doi\":\"10.1109/IMTC.1990.66003\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new strategy of successive approximation for fast analog-to-digital converter (ADC) circuits is discussed. A 4-b converter of one-cycle conversion time is first described. The scheme is then modified for flash conversion. The use of a 4-b flash converter in multiplex mode is shown to result in an 8-b converter requiring half-cycle conversion time. The bit subrangeable flash ADC is presented as an attractive proposal. This scheme essentially requires only two major components per bit and uses n identical circuits in cascade for n-b conversion.<<ETX>>\",\"PeriodicalId\":404761,\"journal\":{\"name\":\"7th IEEE Conference on Instrumentation and Measurement Technology\",\"volume\":\"48 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-02-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"7th IEEE Conference on Instrumentation and Measurement Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMTC.1990.66003\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"7th IEEE Conference on Instrumentation and Measurement Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMTC.1990.66003","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new strategy of successive approximation for fast analog-to-digital converter (ADC) circuits is discussed. A 4-b converter of one-cycle conversion time is first described. The scheme is then modified for flash conversion. The use of a 4-b flash converter in multiplex mode is shown to result in an 8-b converter requiring half-cycle conversion time. The bit subrangeable flash ADC is presented as an attractive proposal. This scheme essentially requires only two major components per bit and uses n identical circuits in cascade for n-b conversion.<>
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