{"title":"倒装芯片设计的单层差分组路由","authors":"I-Jye Lin, Ming Yang, Kai-Shun Hu","doi":"10.1109/VLSI-DAT.2016.7482548","DOIUrl":null,"url":null,"abstract":"This work proposed an entry (merge point) finder for differential group pattern match RDL routing. The entry finder includes a quick routability checker, which can filter out the unroutable merge points to reduce the turnaround time. Besides, this work also proposed a controllable cost function to measure the routing quality of each routing result using different merge points. Thus, the best merge point and routing solution can be easily identified.","PeriodicalId":380961,"journal":{"name":"2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Single layer differential group routing for flip-chip designs\",\"authors\":\"I-Jye Lin, Ming Yang, Kai-Shun Hu\",\"doi\":\"10.1109/VLSI-DAT.2016.7482548\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work proposed an entry (merge point) finder for differential group pattern match RDL routing. The entry finder includes a quick routability checker, which can filter out the unroutable merge points to reduce the turnaround time. Besides, this work also proposed a controllable cost function to measure the routing quality of each routing result using different merge points. Thus, the best merge point and routing solution can be easily identified.\",\"PeriodicalId\":380961,\"journal\":{\"name\":\"2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-04-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-DAT.2016.7482548\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT.2016.7482548","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Single layer differential group routing for flip-chip designs
This work proposed an entry (merge point) finder for differential group pattern match RDL routing. The entry finder includes a quick routability checker, which can filter out the unroutable merge points to reduce the turnaround time. Besides, this work also proposed a controllable cost function to measure the routing quality of each routing result using different merge points. Thus, the best merge point and routing solution can be easily identified.