采用28nm 3.6GHz 128线程SPARC T5处理器及系统应用

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2013-12-23 DOI:10.1109/ASSCC.2013.6690971

V. Krishnaswamy, Jinuk Luke Shin, Sebastian Turullols, J. Hart, G. Konstadinidis, Dawei Huang

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引用次数: 0

摘要

SPARC T5处理器实现了16个8线程的SPARC S3内核，一个8mb的16路集合关联L3缓存，8个BL8 DDR3-1066调度器，以及集成的PCIe Gen-3。该处理器将上一代SPARC T4 CPU的性能提高了一倍，并以单跳无胶方式扩展了对多达8个插槽系统的支持。它采用台积电28纳米工艺，使用15亿个晶体管和13层金属堆叠。该芯片的最大工作频率为3.6 GHz。

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A 28nm 3.6GHz 128 thread SPARC T5 processor and system applications

The SPARC T5 processor implements 16 8-threaded SPARC S3 cores, an 8-MB 16-way set-associative L3 cache, 8 BL8 DDR3-1066 schedulers, and integrated PCIe Gen-3. The processor doubles the performance of the previous generation SPARC T4 CPU and expands support for up to 8 socket systems in a single hop glueless fashion. It is implemented in the TSMC 28nm process using 1.5 billion transistors and a 13 layer metal stack. The chip has a maximum operating frequency of 3.6 GHz.

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来源期刊

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)

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