40nm制程0.6 V亚阈值运算放大器的设计

Khristopherson C. Cajucom, F. Cruz, G. Magwili
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引用次数: 0

摘要

运算放大器是模拟设计中最有用和最基本的电路模块之一。随着技术的不断进步,大多数应用,特别是医疗保健领域,对模拟前端运算放大器设计提出了低电压和低功耗的要求。随着工艺技术的日益小型化,MOS晶体管可以在更小的VGS、VTH和VDS电压下工作。本研究的重点是设计一个能在低功耗条件下工作在0.6 V电源电压下的运算放大器,使用40纳米工艺技术在亚阈值区域工作。所提出的电路功耗小于10 uW,输出漂移为13 uV/°C。设计模拟使用蒙特卡罗由于简单,优化和直接的近似解。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design of 0.6 V Sub-Threshold Operational Amplifier in 40 Nm Process
Operational amplifiers are one of the most useful and basic circuit building blocks for analog design. With the continuous technological advancement, most applications, especially on healthcare, demanded low voltage and low power consumption for analog front-end op-amp design. As process technology has become increasingly smaller, the MOS transistors can operate at smaller VGS, VTH, and VDS voltage. This study focuses on designing an op-amp capable of operating at 0.6 V supply voltage under low power condition using sub-threshold region of operation using the 40 nm process technology. The proposed circuit has less than 10 uW power consumption with 13 uV/° $C$ output drift. Design simulation using Monte Carlo is used due to simplicity, optimization and straight forward approximate solution.
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