Hardware Design and Optimization of Polynomial Multiplication for Post-Quantum Cryptography Algorithm Based on NTT

The Number Theoretical Transform (NTT) plays a crucial role in post-quantum cryptography algorithms, with its computational performance directly impacting system operating speed. This article proposes a high-performance NTT hardware architecture based on a pipeline architecture to address the challenges of lengthy computing processes and complex control logic in NTT hardware implementation. Firstly, a recursive NTT is advanced to simplify the calculation process and facilitate hardware implementation. Next, effective pipeline segmentation is applied to the computing process to reduce hardware architecture complexity. Finally, a two-stage butterfly operation is employed to implement butterfly elements, and the reduction calculation process is optimized using shift and addition, resulting in reduced hardware resource costs. The proposed NTT hardware architecture is implemented on Quartus II (EP2AGZ225FF35C3) taking the CRYSTALS-Kyber anti-quantum cryptography scheme as an example, since the selected prime number can meet requirements. Experimental results demonstrate that the proposed design outperforms other related designs in terms of computational performance and hardware overhead.