Tatsuya Maekawa, Y. Miwa, Akihito Uno, Daisuke Ito, Makoto Nakamura
{"title":"远距离PON系统中下游数据的可调预强调架构","authors":"Tatsuya Maekawa, Y. Miwa, Akihito Uno, Daisuke Ito, Makoto Nakamura","doi":"10.1109/ISOCC47750.2019.9027711","DOIUrl":null,"url":null,"abstract":"The proposed architecture estimates the pre-emphasis weighting of the transmitter from the waveform monitor in the receiver. This weighting data is stored on the memory, and it makes a quick response to packet data. We evaluated the proposed circuit with a field programmable gate array (FPGA), and it achieved good eye openings with high-speed response for wide degradation conditions.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Tunable pre-emphasis architecture for downstream data in long-haul PON systems\",\"authors\":\"Tatsuya Maekawa, Y. Miwa, Akihito Uno, Daisuke Ito, Makoto Nakamura\",\"doi\":\"10.1109/ISOCC47750.2019.9027711\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The proposed architecture estimates the pre-emphasis weighting of the transmitter from the waveform monitor in the receiver. This weighting data is stored on the memory, and it makes a quick response to packet data. We evaluated the proposed circuit with a field programmable gate array (FPGA), and it achieved good eye openings with high-speed response for wide degradation conditions.\",\"PeriodicalId\":113802,\"journal\":{\"name\":\"2019 International SoC Design Conference (ISOCC)\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC47750.2019.9027711\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC47750.2019.9027711","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Tunable pre-emphasis architecture for downstream data in long-haul PON systems
The proposed architecture estimates the pre-emphasis weighting of the transmitter from the waveform monitor in the receiver. This weighting data is stored on the memory, and it makes a quick response to packet data. We evaluated the proposed circuit with a field programmable gate array (FPGA), and it achieved good eye openings with high-speed response for wide degradation conditions.