{"title":"机器人光通信与传感用降噪连续σ - δ调制器的设计","authors":"W. Lai","doi":"10.1109/ARIS50834.2020.9205776","DOIUrl":null,"url":null,"abstract":"The proposed continuous-time sigma-delta $(\\Sigma\\Delta)$ modulator employing nonreturn-to-zero (NRZ) digital-to-analog converter (DAC) and pulse shaping to achieve the performance of reducing the impact of clock jitter noise reduction is presented. The proposed modulator comprises a third order RC operational-amplifier-based loop filter, 4-bit internal quantizer operating at 160 MHz and three DACs. The NRZ DAC with quantizer excess loop delay compensation is set to be half the sampling period of the quantizer. The $\\Sigma\\Delta$ modulator dissipates 10.1 mW at 1.2 V supply voltage is implemented in the TSMC 0.18 um CMOS technology for robotic light communication and intelligent sensor fusion. Measured results illustrate that the $\\Sigma\\Delta$ modulator achieves 66.9 dB SNR, a peak 62 dB SNDR and 10.3 ENOB over a 10 MHz band at an over-sampling ratio (OSR) of 8. Including pads, the chip dimension is $0.363mm^{2}.$","PeriodicalId":423389,"journal":{"name":"2020 International Conference on Advanced Robotics and Intelligent Systems (ARIS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of Continuous-Time Sigma-Delta Modulator with Noise Reduction for Robotic Light Communication and Sensing\",\"authors\":\"W. Lai\",\"doi\":\"10.1109/ARIS50834.2020.9205776\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The proposed continuous-time sigma-delta $(\\\\Sigma\\\\Delta)$ modulator employing nonreturn-to-zero (NRZ) digital-to-analog converter (DAC) and pulse shaping to achieve the performance of reducing the impact of clock jitter noise reduction is presented. The proposed modulator comprises a third order RC operational-amplifier-based loop filter, 4-bit internal quantizer operating at 160 MHz and three DACs. The NRZ DAC with quantizer excess loop delay compensation is set to be half the sampling period of the quantizer. The $\\\\Sigma\\\\Delta$ modulator dissipates 10.1 mW at 1.2 V supply voltage is implemented in the TSMC 0.18 um CMOS technology for robotic light communication and intelligent sensor fusion. Measured results illustrate that the $\\\\Sigma\\\\Delta$ modulator achieves 66.9 dB SNR, a peak 62 dB SNDR and 10.3 ENOB over a 10 MHz band at an over-sampling ratio (OSR) of 8. Including pads, the chip dimension is $0.363mm^{2}.$\",\"PeriodicalId\":423389,\"journal\":{\"name\":\"2020 International Conference on Advanced Robotics and Intelligent Systems (ARIS)\",\"volume\":\"34 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 International Conference on Advanced Robotics and Intelligent Systems (ARIS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ARIS50834.2020.9205776\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International Conference on Advanced Robotics and Intelligent Systems (ARIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARIS50834.2020.9205776","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
提出了一种采用非归零(NRZ)数模转换器(DAC)和脉冲整形的连续时间sigma-delta $(\Sigma\Delta)$调制器,以达到降低时钟抖动降噪影响的性能。所提出的调制器包括一个基于三阶RC运算放大器的环路滤波器、工作频率为160 MHz的4位内部量化器和三个dac。采用量化器补偿多余环路延迟的NRZ DAC设置为量化器采样周期的一半。$\Sigma\Delta$调制器在1.2 V电源电压下耗电10.1 mW,采用台积电0.18 um CMOS技术,用于机器人光通信和智能传感器融合。测量结果表明,$\Sigma\Delta$调制器在过采样比(OSR)为8的情况下,在10 MHz频段内实现了66.9 dB信噪比,峰值62 dB SNDR和10.3 ENOB。包括衬垫在内,芯片尺寸为 $0.363mm^{2}.$
Design of Continuous-Time Sigma-Delta Modulator with Noise Reduction for Robotic Light Communication and Sensing
The proposed continuous-time sigma-delta $(\Sigma\Delta)$ modulator employing nonreturn-to-zero (NRZ) digital-to-analog converter (DAC) and pulse shaping to achieve the performance of reducing the impact of clock jitter noise reduction is presented. The proposed modulator comprises a third order RC operational-amplifier-based loop filter, 4-bit internal quantizer operating at 160 MHz and three DACs. The NRZ DAC with quantizer excess loop delay compensation is set to be half the sampling period of the quantizer. The $\Sigma\Delta$ modulator dissipates 10.1 mW at 1.2 V supply voltage is implemented in the TSMC 0.18 um CMOS technology for robotic light communication and intelligent sensor fusion. Measured results illustrate that the $\Sigma\Delta$ modulator achieves 66.9 dB SNR, a peak 62 dB SNDR and 10.3 ENOB over a 10 MHz band at an over-sampling ratio (OSR) of 8. Including pads, the chip dimension is $0.363mm^{2}.$