Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, R. Theertham, S. Pavan, Lu Jie, Nan Sun
{"title":"基于低成本二阶矢量量化DEM的0.37mm2 250kHz-BW 95dB-SNDR CTDSM","authors":"Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, R. Theertham, S. Pavan, Lu Jie, Nan Sun","doi":"10.1109/CICC53496.2022.9772865","DOIUrl":null,"url":null,"abstract":"CTDSMs with high resolution and bandwidth greater than 200kHz are needed in industrial, medical, and automotive applications. Such high performance demands very low noise and distortion. The noise and distortion have to be suppressed even further in advanced technologies due to the low voltage headroom. A major challenge of low noise and distortion design is the large area cost of DAC and loop filters. The main feedback RDAC occupies a large area in [1]. 1st-order data weighted average (DWA) is used but has limited mismatch error suppression. There is also a kink in the SNDR plot of [1] at low input amplitudes due to tones caused by DWA. To reduce the area, [2], [3] use DWA for the MSB bits and mismatch error shaping (MES) for the LSB bits. MES enables the binary coded DAC to save the LSB DAC area. However, the overall DAC's mismatch-induced distortion is dominated by the MSB bits. Thus, the approach of [2], [3] yields limited performance benefits due to the relatively mild 1st-order mismatch error shaping obtained from the DWA operation on the MSB bits.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 0.37mm2 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2nd-order Vector-Quantizer DEM\",\"authors\":\"Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, R. Theertham, S. Pavan, Lu Jie, Nan Sun\",\"doi\":\"10.1109/CICC53496.2022.9772865\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"CTDSMs with high resolution and bandwidth greater than 200kHz are needed in industrial, medical, and automotive applications. Such high performance demands very low noise and distortion. The noise and distortion have to be suppressed even further in advanced technologies due to the low voltage headroom. A major challenge of low noise and distortion design is the large area cost of DAC and loop filters. The main feedback RDAC occupies a large area in [1]. 1st-order data weighted average (DWA) is used but has limited mismatch error suppression. There is also a kink in the SNDR plot of [1] at low input amplitudes due to tones caused by DWA. To reduce the area, [2], [3] use DWA for the MSB bits and mismatch error shaping (MES) for the LSB bits. MES enables the binary coded DAC to save the LSB DAC area. However, the overall DAC's mismatch-induced distortion is dominated by the MSB bits. Thus, the approach of [2], [3] yields limited performance benefits due to the relatively mild 1st-order mismatch error shaping obtained from the DWA operation on the MSB bits.\",\"PeriodicalId\":415990,\"journal\":{\"name\":\"2022 IEEE Custom Integrated Circuits Conference (CICC)\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Custom Integrated Circuits Conference (CICC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC53496.2022.9772865\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Custom Integrated Circuits Conference (CICC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC53496.2022.9772865","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.37mm2 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2nd-order Vector-Quantizer DEM
CTDSMs with high resolution and bandwidth greater than 200kHz are needed in industrial, medical, and automotive applications. Such high performance demands very low noise and distortion. The noise and distortion have to be suppressed even further in advanced technologies due to the low voltage headroom. A major challenge of low noise and distortion design is the large area cost of DAC and loop filters. The main feedback RDAC occupies a large area in [1]. 1st-order data weighted average (DWA) is used but has limited mismatch error suppression. There is also a kink in the SNDR plot of [1] at low input amplitudes due to tones caused by DWA. To reduce the area, [2], [3] use DWA for the MSB bits and mismatch error shaping (MES) for the LSB bits. MES enables the binary coded DAC to save the LSB DAC area. However, the overall DAC's mismatch-induced distortion is dominated by the MSB bits. Thus, the approach of [2], [3] yields limited performance benefits due to the relatively mild 1st-order mismatch error shaping obtained from the DWA operation on the MSB bits.