{"title":"一个12位电流模式折叠/插值CMOS A/D转换器，具有2步结构","authors":"Hyung Hoon Kim, K. Yoon","doi":"10.1109/APASIC.1999.824056","DOIUrl":null,"url":null,"abstract":"An 12 bit 20 MS/s current-mode folding and interpolation analog to digital converter (ADC) with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current sources, but also to decrease the power dissipation within the ADC. The proposed ADC is implemented by a 0.65 /spl mu/m n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of /spl plusmn/0.5 LSB, an integral nonlinearity (INL) of /spl plusmn/1.0 LSB, the power dissipation of 280 mW with a power supply of 5 V.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 12 bit current-mode folding/interpolation CMOS A/D converter with 2 step architecture\",\"authors\":\"Hyung Hoon Kim, K. Yoon\",\"doi\":\"10.1109/APASIC.1999.824056\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An 12 bit 20 MS/s current-mode folding and interpolation analog to digital converter (ADC) with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current sources, but also to decrease the power dissipation within the ADC. The proposed ADC is implemented by a 0.65 /spl mu/m n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of /spl plusmn/0.5 LSB, an integral nonlinearity (INL) of /spl plusmn/1.0 LSB, the power dissipation of 280 mW with a power supply of 5 V.\",\"PeriodicalId\":346808,\"journal\":{\"name\":\"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-08-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APASIC.1999.824056\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.1999.824056","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 12 bit current-mode folding/interpolation CMOS A/D converter with 2 step architecture
An 12 bit 20 MS/s current-mode folding and interpolation analog to digital converter (ADC) with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current sources, but also to decrease the power dissipation within the ADC. The proposed ADC is implemented by a 0.65 /spl mu/m n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of /spl plusmn/0.5 LSB, an integral nonlinearity (INL) of /spl plusmn/1.0 LSB, the power dissipation of 280 mW with a power supply of 5 V.
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