基于机器学习的亚14nm制程节点工业设计可达性优化

W. Chan, Pei-Hsin Ho, A. Kahng, Prashant Saxena
{"title":"基于机器学习的亚14nm制程节点工业设计可达性优化","authors":"W. Chan, Pei-Hsin Ho, A. Kahng, Prashant Saxena","doi":"10.1145/3036669.3036681","DOIUrl":null,"url":null,"abstract":"Design rule check (DRC) violations after detailed routing prevent a design from being taped out. To solve this problem, state-of-the-art commercial EDA tools global-route the design to produce a global-route congestion map; this map is used by the placer to optimize the placement of the design to reduce detailed-route DRC violations. However, in sub-14nm processes and beyond, DRCs arising from multiple patterning and pin-access constraints drastically weaken the correlation between global-route congestion and detailed-route DRC violations. Hence, the placer|based on the global-route congestion map|may leave too many detailed-route DRC violations to be fixed manually by designers. In this paper, we present a method that employs (1) machine-learning techniques to effectively predict detailed-route DRC violations after global routing and (2) detailed placement techniques to effectively reduce detailed-route DRC violations. We demonstrate on several layouts of a sub-14nm industrial design that this method predicts the locations of 74% of the detailed-route DRCs (with false positive prediction rate below 0.2%) and automatically reduces the number of detailed-route DRC violations by up to 5x. Whereas previous works on machine learning for routability [30] [4] have focused on routability prediction at the floorplanning and placement stages, ours is the first paper that not only predicts the actual locations of detailed-route DRC violations but furthermore optimizes the design to significantly reduce such violations.","PeriodicalId":269197,"journal":{"name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2017-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"70","resultStr":"{\"title\":\"Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning\",\"authors\":\"W. Chan, Pei-Hsin Ho, A. Kahng, Prashant Saxena\",\"doi\":\"10.1145/3036669.3036681\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Design rule check (DRC) violations after detailed routing prevent a design from being taped out. To solve this problem, state-of-the-art commercial EDA tools global-route the design to produce a global-route congestion map; this map is used by the placer to optimize the placement of the design to reduce detailed-route DRC violations. However, in sub-14nm processes and beyond, DRCs arising from multiple patterning and pin-access constraints drastically weaken the correlation between global-route congestion and detailed-route DRC violations. Hence, the placer|based on the global-route congestion map|may leave too many detailed-route DRC violations to be fixed manually by designers. In this paper, we present a method that employs (1) machine-learning techniques to effectively predict detailed-route DRC violations after global routing and (2) detailed placement techniques to effectively reduce detailed-route DRC violations. We demonstrate on several layouts of a sub-14nm industrial design that this method predicts the locations of 74% of the detailed-route DRCs (with false positive prediction rate below 0.2%) and automatically reduces the number of detailed-route DRC violations by up to 5x. Whereas previous works on machine learning for routability [30] [4] have focused on routability prediction at the floorplanning and placement stages, ours is the first paper that not only predicts the actual locations of detailed-route DRC violations but furthermore optimizes the design to significantly reduce such violations.\",\"PeriodicalId\":269197,\"journal\":{\"name\":\"Proceedings of the 2017 ACM on International Symposium on Physical Design\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-03-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"70\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2017 ACM on International Symposium on Physical Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/3036669.3036681\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2017 ACM on International Symposium on Physical Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/3036669.3036681","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 70

摘要

在详细布线后违反设计规则检查(DRC)会阻止设计被贴出。为了解决这个问题,最先进的商业EDA工具全球路由的设计,以产生一个全球路由拥塞图;该地图被砂矿商用来优化设计的位置,以减少详细路线的DRC违规。然而,在14nm以下的工艺中,由多模式和引脚访问约束引起的DRC大大削弱了全局路由拥塞和详细路由DRC违规之间的相关性。因此,基于全局路由拥塞图|的砂子|可能会留下太多的详细路由DRC违规,需要设计者手动修复。在本文中,我们提出了一种方法,该方法使用(1)机器学习技术来有效地预测全局路由后的详细路由DRC违规;(2)详细放置技术来有效地减少详细路由DRC违规。我们在sub-14nm工业设计的几种布局中证明,该方法预测了74%的详细路由DRC的位置(假阳性预测率低于0.2%),并自动将详细路由DRC违规次数减少了5倍。鉴于之前关于可达性的机器学习工作主要集中在平面规划和放置阶段的可达性预测,我们的论文不仅预测了详细路线DRC违规的实际位置,而且进一步优化了设计以显着减少此类违规。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning
Design rule check (DRC) violations after detailed routing prevent a design from being taped out. To solve this problem, state-of-the-art commercial EDA tools global-route the design to produce a global-route congestion map; this map is used by the placer to optimize the placement of the design to reduce detailed-route DRC violations. However, in sub-14nm processes and beyond, DRCs arising from multiple patterning and pin-access constraints drastically weaken the correlation between global-route congestion and detailed-route DRC violations. Hence, the placer|based on the global-route congestion map|may leave too many detailed-route DRC violations to be fixed manually by designers. In this paper, we present a method that employs (1) machine-learning techniques to effectively predict detailed-route DRC violations after global routing and (2) detailed placement techniques to effectively reduce detailed-route DRC violations. We demonstrate on several layouts of a sub-14nm industrial design that this method predicts the locations of 74% of the detailed-route DRCs (with false positive prediction rate below 0.2%) and automatically reduces the number of detailed-route DRC violations by up to 5x. Whereas previous works on machine learning for routability [30] [4] have focused on routability prediction at the floorplanning and placement stages, ours is the first paper that not only predicts the actual locations of detailed-route DRC violations but furthermore optimizes the design to significantly reduce such violations.
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