有源rc连续时间DSM与FIR+可控硅DAC

2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2017-10-01 DOI:10.1109/EDSSC.2017.8126573

Yang Zhang, D. Basak, Daxiang Li, K. Pun

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引用次数: 0

摘要

本文提出在σ δ调制器中使用FIR+SC DAC是一种平衡对时钟抖动噪声不敏感和功率效率的方法。在UMC 180nm工艺上实现了一个实例，仿真结果表明，在100kHz带宽下，SNDR达到77.2dB，功耗为83 μW，对应于FoMw 71fJ/conv。

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Active-RC continuous-time DSM with FIR+SCR DAC

This paper proposes the use of FIR+SC DAC in sigma delta modulator is an approach to balance insensitivity to clock jitter noise and power efficiency. An example is implemented in UMC 180nm technology and simulation results show that it achieves SNDR 77.2dB and 83 μW power consumption in 100kHz bandwidth, which corresponds to FoMw 71fJ/conv.

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2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)

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