{"title":"一个高度可扩展的系统,利用多达128个PA-RISC处理器","authors":"Tony M. Brewer","doi":"10.1109/CMPCON.1995.512376","DOIUrl":null,"url":null,"abstract":"A highly scalable system implementing Convex's Exemplar Architecture has been designed. The system allows up to 128 Hewlett-Packard processors to efficiently cooperate together. All processors may be used together to substantially decrease the time-to-solution for large applications, or the processors may be used in smaller subsets in a time-sharing parallel environment. The system has many features which enhance the parallel usability of the system. These features include globally shared memory, interconnect caches, memory massed semaphores, and hardware messaging support.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"A highly scalable system utilizing up to 128 PA-RISC processors\",\"authors\":\"Tony M. Brewer\",\"doi\":\"10.1109/CMPCON.1995.512376\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A highly scalable system implementing Convex's Exemplar Architecture has been designed. The system allows up to 128 Hewlett-Packard processors to efficiently cooperate together. All processors may be used together to substantially decrease the time-to-solution for large applications, or the processors may be used in smaller subsets in a time-sharing parallel environment. The system has many features which enhance the parallel usability of the system. These features include globally shared memory, interconnect caches, memory massed semaphores, and hardware messaging support.\",\"PeriodicalId\":415918,\"journal\":{\"name\":\"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-03-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CMPCON.1995.512376\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CMPCON.1995.512376","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A highly scalable system utilizing up to 128 PA-RISC processors
A highly scalable system implementing Convex's Exemplar Architecture has been designed. The system allows up to 128 Hewlett-Packard processors to efficiently cooperate together. All processors may be used together to substantially decrease the time-to-solution for large applications, or the processors may be used in smaller subsets in a time-sharing parallel environment. The system has many features which enhance the parallel usability of the system. These features include globally shared memory, interconnect caches, memory massed semaphores, and hardware messaging support.