{"title":"射频CMOS开关功率放大器的寄生感知合成","authors":"Kiyong Choi, D. Allstot, S. Kiaei","doi":"10.1109/ISCAS.2002.1009829","DOIUrl":null,"url":null,"abstract":"Parasitic-aware synthesis and optimization techniques are presented for a 0.35 /spl mu/m CMOS three-stage 1 W 900 MHz class-E power amplifier. Employing bond wire and spiral inductors, it achieves 25 dB gain with 49% drain efficiency from a 3.3 V supply. Simulated annealing optimization is used taking advantage of its ability to escape local minima.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"53 1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"Parasitic-aware synthesis of RF CMOS switching power amplifiers\",\"authors\":\"Kiyong Choi, D. Allstot, S. Kiaei\",\"doi\":\"10.1109/ISCAS.2002.1009829\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Parasitic-aware synthesis and optimization techniques are presented for a 0.35 /spl mu/m CMOS three-stage 1 W 900 MHz class-E power amplifier. Employing bond wire and spiral inductors, it achieves 25 dB gain with 49% drain efficiency from a 3.3 V supply. Simulated annealing optimization is used taking advantage of its ability to escape local minima.\",\"PeriodicalId\":203750,\"journal\":{\"name\":\"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)\",\"volume\":\"53 1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2002.1009829\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2002.1009829","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Parasitic-aware synthesis of RF CMOS switching power amplifiers
Parasitic-aware synthesis and optimization techniques are presented for a 0.35 /spl mu/m CMOS three-stage 1 W 900 MHz class-E power amplifier. Employing bond wire and spiral inductors, it achieves 25 dB gain with 49% drain efficiency from a 3.3 V supply. Simulated annealing optimization is used taking advantage of its ability to escape local minima.