{"title":"专用阵列处理器实现的神经网络","authors":"S. Kung, J. Vlontzos","doi":"10.1109/TAI.1990.130322","DOIUrl":null,"url":null,"abstract":"A universal digital VLSI design for implementing artificial neural networks is proposed. The design is based on a unified iterative neural network model. An implementation based on a combination of custom-built and commercially available chips is presented. In addition, a software environment for the array processor is discussed.<<ETX>>","PeriodicalId":366276,"journal":{"name":"[1990] Proceedings of the 2nd International IEEE Conference on Tools for Artificial Intelligence","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Special purpose array processor implementation of neural networks\",\"authors\":\"S. Kung, J. Vlontzos\",\"doi\":\"10.1109/TAI.1990.130322\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A universal digital VLSI design for implementing artificial neural networks is proposed. The design is based on a unified iterative neural network model. An implementation based on a combination of custom-built and commercially available chips is presented. In addition, a software environment for the array processor is discussed.<<ETX>>\",\"PeriodicalId\":366276,\"journal\":{\"name\":\"[1990] Proceedings of the 2nd International IEEE Conference on Tools for Artificial Intelligence\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-11-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1990] Proceedings of the 2nd International IEEE Conference on Tools for Artificial Intelligence\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TAI.1990.130322\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1990] Proceedings of the 2nd International IEEE Conference on Tools for Artificial Intelligence","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TAI.1990.130322","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Special purpose array processor implementation of neural networks
A universal digital VLSI design for implementing artificial neural networks is proposed. The design is based on a unified iterative neural network model. An implementation based on a combination of custom-built and commercially available chips is presented. In addition, a software environment for the array processor is discussed.<>