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引用次数: 10
摘要
本文介绍了基于ARM926EJS仿真基板的硬件JPEG编解码器的设计和性能测试。JPEG是静止图像最好的压缩算法之一。高压缩比，保持高质量。JPEG编解码器对彩色和灰色图像格式进行编码和解码。该设计利用流水线架构实现高吞吐量。通过共享JPEG编码器和解码器之间的公共资源来控制编解码器的总体大小。在ARM926EJS仿真基板上为Xilinx™Virtex II FPGA器件合成了硬件JPEG编解码器。本文涵盖了为性能测量所做的所有RTL修改。FPGA资源利用率在合成后和映射后阶段被制成表格。对彩色和灰色图像的编码器和解码器进行了实时性能测量。
Performance measurement of a fully pipelined JPEG codec on emulation platform
This paper presents the design and performance measurement of the hardware JPEG codec on an ARM926EJS emulation base board. JPEG is one of the best compression algorithms for still images. It preserves the quality with high compression ratio. JPEG codec encodes and decodes coloured as well grey image formats. The design exploits the pipeline architecture for high throughput. Overall size of the codec is controlled by sharing the common resources between JPEG encoder and decoder. Hardware JPEG codec was synthesized for Xilinx™ Virtex II FPGA device on ARM926EJS emulation base board. The paper covers all the RTL modifications done for performance measurement. FPGA resource utilization is tabulated at post-synthesis and post-mapping stage. Real time performance measurement is done for encoder and decoder for colored and grey images.
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