QCA中5输入多数门全加减法器的高效设计

Ramanand Jaiswal, T. Sasamal
{"title":"QCA中5输入多数门全加减法器的高效设计","authors":"Ramanand Jaiswal, T. Sasamal","doi":"10.1109/IC3.2017.8284336","DOIUrl":null,"url":null,"abstract":"Quantum dot cellular automata is the recent trend in the field of technology for the designing of any digital circuit involving inverters and majority gates that has the potential to substitute the age old technology of CMOS at the order of Nano level. Herein a full adder and full subtractor circuit is proposed using 5-input majority gate. The new full adder and subtractor reduced the requirement of occupied area, number of cells and energy dissipation. QCAPro tool is used for the calculation of energy dissipation. QCA designer 2.0.3 is used to design and simulate the circuits. A 4-bit ripple carry adder is also designed by one bit full adder.","PeriodicalId":147099,"journal":{"name":"2017 Tenth International Conference on Contemporary Computing (IC3)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"23","resultStr":"{\"title\":\"Efficient design of full adder and subtractor using 5-input majority gate in QCA\",\"authors\":\"Ramanand Jaiswal, T. Sasamal\",\"doi\":\"10.1109/IC3.2017.8284336\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Quantum dot cellular automata is the recent trend in the field of technology for the designing of any digital circuit involving inverters and majority gates that has the potential to substitute the age old technology of CMOS at the order of Nano level. Herein a full adder and full subtractor circuit is proposed using 5-input majority gate. The new full adder and subtractor reduced the requirement of occupied area, number of cells and energy dissipation. QCAPro tool is used for the calculation of energy dissipation. QCA designer 2.0.3 is used to design and simulate the circuits. A 4-bit ripple carry adder is also designed by one bit full adder.\",\"PeriodicalId\":147099,\"journal\":{\"name\":\"2017 Tenth International Conference on Contemporary Computing (IC3)\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"23\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Tenth International Conference on Contemporary Computing (IC3)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IC3.2017.8284336\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Tenth International Conference on Contemporary Computing (IC3)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IC3.2017.8284336","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 23

摘要

量子点元胞自动机是设计任何涉及逆变器和多数门的数字电路的技术领域的最新趋势,它有可能在纳米级上取代古老的CMOS技术。本文提出了一种采用5输入多数门的全加、全减电路。新的全加减法器减少了对占用面积、单元数和能量消耗的要求。耗能计算采用QCAPro工具。采用QCA设计器2.0.3对电路进行设计和仿真。采用1位全加法器设计了4位纹波进位加法器。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Efficient design of full adder and subtractor using 5-input majority gate in QCA
Quantum dot cellular automata is the recent trend in the field of technology for the designing of any digital circuit involving inverters and majority gates that has the potential to substitute the age old technology of CMOS at the order of Nano level. Herein a full adder and full subtractor circuit is proposed using 5-input majority gate. The new full adder and subtractor reduced the requirement of occupied area, number of cells and energy dissipation. QCAPro tool is used for the calculation of energy dissipation. QCA designer 2.0.3 is used to design and simulate the circuits. A 4-bit ripple carry adder is also designed by one bit full adder.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信