基于FPGA架构的YOLO加速

Guangju Wei, Yanzhao Hou, Qimei Cui, Gang Deng, Xiaofeng Tao, Y. Yao
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引用次数: 8

摘要

近年来,卷积神经网络(CNN)取得了突破性的发展。然而,随着CNN的空间复杂度和时间复杂度的逐渐增加,在移动应用中实现更大规模的CNN是一个巨大的挑战。基于fpga的加速平台因其高性能、低功耗、可重构等优点而逐渐受到研究。本文基于Xillinx公司发布的Zynq板实现了YOLO平台,并结合FPGA的特点对其架构进行了优化。在行人和汽车识别的实时用例中,该方法优于传统的基于cpu的YOLO网络。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
YOLO Acceleration using FPGA Architecture
In recent years, convolutional neural networks (CNN) have achieved breakthrough developments. However, with the spatial and time complexity of CNN gradually increasing, it becomes a great challenge to implement larger CNN for mobile applications. Accelerated platforms based on FPGAs are gradually being studied due to its advantages such as high performance, low power consumption, reconfigurability, etc. In this paper, we implement the YOLO platform based on the Zynq board (which is released by Xillinx) and optimize its architecture combined the FPGA feature. The use case of pedestrian and cars recognition is demonstrated in real time, which outperforms the traditional CPU-based YOLO networks.
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