有效的电子实现改进的符号数位免进位加法器

Proceedings of the IEEE 1993 National Aerospace and Electronics Conference-NAECON 1993 Pub Date : 1993-05-24 DOI:10.1109/NAECON.1993.290913

M. M. Hossain, J. U. Ahmed, A. Awwal

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引用次数: 7

摘要

提出了一种可用于并行计算的改进的无进位加、免借三进位减方案。利用电可编程逻辑器件(EPLD)设计并实现了一个2位数字加法器原型

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Efficient electronic implementation of modified signed-digit trinary carry free adder

An efficient carry-free addition and borrow-free subtraction of modified signed-digit trinary number scheme is presented which may be used for parallel computing application. A digital 2 bit prototype adder was designed and implemented using electrically programmable logic device (EPLD).<>

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来源期刊

Proceedings of the IEEE 1993 National Aerospace and Electronics Conference-NAECON 1993

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