Tiedong Wang, Fengjing Shao, Rencheng Sun, He Huang
{"title":"基于单CPU双总线结构的总线桥的硬件实现","authors":"Tiedong Wang, Fengjing Shao, Rencheng Sun, He Huang","doi":"10.1109/ISCSCT.2008.106","DOIUrl":null,"url":null,"abstract":"Single CPU dual bus architecture is a new kind of architecture aimed at reducing the security vulnerability of Von Neumann architecture, and it has been proved theoretically reasonable. In this paper, a bus bridge is implemented to bridge CPU and dual bus. The experiment is done and the result has proved that the architecture based on single CPU and dual bus is reasonable and effective.","PeriodicalId":228533,"journal":{"name":"2008 International Symposium on Computer Science and Computational Technology","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"A Hardware Implement of Bus Bridge Based on Single CPU and Dual Bus Architecture\",\"authors\":\"Tiedong Wang, Fengjing Shao, Rencheng Sun, He Huang\",\"doi\":\"10.1109/ISCSCT.2008.106\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Single CPU dual bus architecture is a new kind of architecture aimed at reducing the security vulnerability of Von Neumann architecture, and it has been proved theoretically reasonable. In this paper, a bus bridge is implemented to bridge CPU and dual bus. The experiment is done and the result has proved that the architecture based on single CPU and dual bus is reasonable and effective.\",\"PeriodicalId\":228533,\"journal\":{\"name\":\"2008 International Symposium on Computer Science and Computational Technology\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-12-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 International Symposium on Computer Science and Computational Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCSCT.2008.106\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International Symposium on Computer Science and Computational Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCSCT.2008.106","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Hardware Implement of Bus Bridge Based on Single CPU and Dual Bus Architecture
Single CPU dual bus architecture is a new kind of architecture aimed at reducing the security vulnerability of Von Neumann architecture, and it has been proved theoretically reasonable. In this paper, a bus bridge is implemented to bridge CPU and dual bus. The experiment is done and the result has proved that the architecture based on single CPU and dual bus is reasonable and effective.