S. Honda, Y. Haraguchi, A. Narazaki, T. Terashima, Y. Terasaki
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Next generation 600V CSTBT™ with an advanced fine pattern and a thin wafer process technologies
In this paper, we present the characteristics of a fabricated 600V CSTBT™ as the next generation IGBT. The techniques applied this novel device include about half-size shrinkage of the transistor unit cell with a fine pattern process and an LPT (Light Punch Through) structure utilizing an advanced thin wafer process technology. As a result, these techniques brought a significant reduction of the Vce(sat) and the Eoff. The Vce(sat)-Eoff trade-off relationship of the proposed CSTBT has been improved by approximately 20% compared to the conventional one possessing wide SOA (Safe Operating Area) enough to device applications.
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